In charge-domain signal-processing circuits, signals are represented as charge packets. These charge packets are stored, transferred from one storage location to another, and otherwise processed to carry out specific signal-processing functions. Charge packets are capable of representing analog quantities, with the charge-packet size in coulombs being proportional to the signal represented. Charge-domain operations such as charge-transfer are driven by ‘clock’ voltages, providing discrete-time processing. Thus, charge-domain circuits provide analog, discrete-time signal-processing capability. This capability is well-suited to performing analog-to-digital conversion using pipeline algorithms.
Charge-domain circuits are implemented as charge-coupled devices (CCDs), as MOS bucket-brigade devices (BBDs), and as bipolar BBDs. The present invention pertains to MOS BBDs.
Pipelined analog-to-digital converters (ADCs) are well-known in the general field of ADC design. They are widely used in applications in which high sample rates and high resolution must be combined. Pipelined ADCs implement the well-known successive-approximation analog-to-digital (A/D) conversion algorithm, in which progressively-refined estimates of an input signal are made at sequential times. In pipelined versions of this algorithm, one or several bits are resolved at each pipeline stage, the quantized estimate is subtracted from the signal, and the residue is propagated to the next pipeline stage for further processing. Pipelined ADCs have been implemented using a variety of circuit techniques, including switched-capacitor circuits and charge-domain circuits. The present invention pertains to charge-domain pipelined ADCs employing MOS BBDs.